1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a semiconductor memory device in which a contact hole for exposing an active region of a semiconductor substrate is self-aligned and ions are locally implanted only on a channel region.
2. Description of the Related Art
As semiconductor memory devices become more highly integrated, the size of a unit cell becomes smaller. In particular, as the size of a cell transistor becomes smaller, short-channel effects such as lowering of threshold voltage and increase in leakage current cause dynamic refresh of a dynamic random access memory (DRAM) to be deteriorated. In order to solve this problem, there is a method for increasing a threshold voltage in which N-type (or P-type) impurity ions are implanted on a substrate before forming a gate electrode in a N-channel transistor (or P-channel transistor), and the concentration of impurities on the substrate is increased.
Also, in order to form P-type (or N-type) source and drain regions on a channel region of the N-channel transistor (or P-channel transistor), the concentration of impurities on the source and drain regions must be larger than the concentration of impurities on the channel region. However, when the size of the transistor becomes smaller, the concentration of ion implantation impurities for suppressing change in the threshold voltage due to the short-channel effect must be increased. Thus, a difference in the concentration of impurities between the source and drain regions of the transistor and the channel region of the transistor is reduced by an increase in integration. Accordingly, junction capacitance between the source and drain regions and the channel region is increased, and the operation speed of the transistor is reduced.
Further, since the concentration of impurity ions for controlling the threshold voltage of the substrate (or well formed on the substrate) is increased by the increase in integration, the junction capacitance is increased by the increase in integration, and a leakage current flowing into the substrate (or well) from the source and drain regions is increased.
A local implantation technology for locally forming an impurity region only on a lower portion of the channel region of the transistor has been developed in solving these problems. However, as the semiconductor memory devices become more highly integrated, it becomes more difficult to manufacture a mask for covering only a portion where a gate electrode is formed. Also, it becomes difficult to obtain a process margin for misalignment in forming a contact hole for use in a plug connecting an active region on the substrate to a bit line, a capacitor or a metal wiring which are formed later.
To solve the above problems, it is an object of the present invention to provide a method for forming a contact hole of a semiconductor memory device capable of obtaining a process margin for misalignment.
It is another object of the present invention to provide a method for forming an impurity region only on a lower portion of a gate electrode of the semiconductor memory device, that is, only on a channel region of the semiconductor memory device.
In accordance with the invention, there is provided a method for manufacturing a semiconductor memory device. A semiconductor substrate comprising an active region and an inactive region is provided. A transistor is formed in the substrate. The transistor has a gate electrode structure including a gate electrode formed of a polysilicon pattern, a spacer formed on a sidewall of the gate electrode, and a source and drain regions in the active region. A refractory metal silicide layer pattern is formed on an upper surface of the polysilicon layer pattern, and a refractory metal silicide layer is formed on an upper surface of the semiconductor substrate on the source and drain regions. An interdielectric layer of a material having a high etching selection ratio with respect to a material forming the spacer, is formed on the entire surface of the semiconductor substrate on which the refractory metal suicide layer pattern and the refractory metal suicide layer are formed. A mask for exposing the active region is formed on the interdielectric layer. An etching process using the mask is performed to form a contact hole for exposing the upper surface of the refractory metal silicide layer pattern and the refractory metal silicide layer. The contact hole is filled with metal to form a contact plug.
In one embodiment, an etch stop layer is formed on the entire surface of the semiconductor substrate after forming the refractory metal silicide layer pattern and the refractory metal silicide layer and before forming the interdielectric layer.
The refractory metal can include Co or Ti, and the refractory metal silicide layer pattern and the refractory metal silicide layer can include CoSix or TiSix. The spacer can be formed of silicon nitride film, aluminum oxide film, or tantalum oxide film, and the interdielectric layer can be formed of a material different from the spacer and can be a silicon oxide film, a silicon nitride film, an undoped silicate glass (USG) film, a phosphosilicate glass (PSG) film, a borosilicate glass (BSG) film, a borophosphosilicate galss (BPSG) film, a tetraethylorthosilicate glass (TEOS) film, an ozone-TEOS film, a plasma enhanced (PE)-TEOS film, or a combination film of these films. The etch stop layer can be a silicon oxynitride film.
In one embodiment, the method can also include implanting ions having the same conductivity type as that of the semiconductor substrate on the active region and forming an impurity region on the semiconductor substrate arranged on a lower portion of the gate electrode structure, after forming the contact plug. The contact plug can be formed of W, Al, or Cu, or a combination film of W, Al, and Cu.